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hc05e1grs/d rev. 2.0 non-disclosure agreement required 68HC05E1 general release specification f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
non-disclosure agreement required general release speci?cation general release specification mc68HC05E1 rev. 2.0 motorola reserves the right to make changes without further notice to any products herein to improve reliability, function or design. motorola does not assume any liability arising out of the application or use of any product or circuit described herein; neither does it convey any license under its patent rights nor the rights of others. motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the motorola product could create a situation where personal injury or death may occur. should buyer purchase or use motorola products for any such unintended or unauthorized application, buyer shall indemnify and hold motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that motorola was negligent regarding the design or manufacture of the part. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
mc68HC05E1 revision 2.0 general release speci?cation table of contents general release specification mc68HC05E1 table of contents section 1. general description 1.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 1.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 1.3 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 1.4 mask options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 1.5 functional pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 1.5.1 v dd and v ss . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 1.5.2 irq (maskable interrupt request) . . . . . . . . . . . . . . . . . . . .16 1.5.3 osc1, osc2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 1.5.3.1 crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 1.5.3.2 ceramic resonator . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 1.5.3.3 external clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 1.5.4 reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 1.5.5 pa0-pa7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 1.5.6 pb0-pb7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 1.5.7 pc0-pc3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 1.5.8 xfc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 1.5.9 v ddsyn . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 section 2. operating modes 2.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 2.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 2.3 single-chip mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 2.4 self-check mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 2.4.1 timer test subroutine . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 2.4.2 rom checksum subroutine. . . . . . . . . . . . . . . . . . . . . . . . .24 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
general release speci?cation mc68HC05E1 revision 2.0 table of contents table of contents 2.4.3 additional self-check routines . . . . . . . . . . . . . . . . . . . . . .25 2.4.3.1 self-check pll disabled . . . . . . . . . . . . . . . . . . . . . . . . .26 2.4.3.2 jump to ram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26 2.4.3.3 load ram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26 section 3. cpu core 3.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 3.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 3.3 registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 3.3.1 accumulator (a) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 3.3.2 index register (x) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29 3.3.3 condition code register (ccr) . . . . . . . . . . . . . . . . . . . . . .29 3.3.3.1 half carry (h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29 3.3.3.2 interrupt (i) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29 3.3.3.3 negative (n) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29 3.3.3.4 zero (z) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30 3.3.3.5 carry/borrow (c) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30 3.3.4 stack pointer (sp) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30 3.3.5 program counter (pc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31 3.4 instruction set. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31 3.4.1 register/memory instructions. . . . . . . . . . . . . . . . . . . . . . . .32 3.4.2 read-modify-write instructions . . . . . . . . . . . . . . . . . . . . . .33 3.4.3 branch instructions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34 3.4.4 bit manipulation instructions . . . . . . . . . . . . . . . . . . . . . . . .35 3.4.5 control instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36 3.5 addressing modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37 3.5.1 immediate. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37 3.5.2 direct . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37 3.5.3 extended . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37 3.5.4 re;atove . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38 3.5.5 indexed, no offset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38 3.5.6 indexed, 8-bit offset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38 3.5.7 indexed, 16-bit offset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39 3.5.8 bit set/clear . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
table of contents mc68HC05E1 revision 2.0 general release speci?cation table of contents 3.5.9 bit test and branch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39 3.5.10 inherent . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40 3.6 resets. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40 3.6.1 power-on reset (por) . . . . . . . . . . . . . . . . . . . . . . . . . . . .40 3.6.2 reset pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40 3.6.3 computer operating properly (cop) reset . . . . . . . . . . . . .40 3.6.4 illegal address reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41 3.7 interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41 3.7.1 hardware controlled interrupt sequence. . . . . . . . . . . . . . .42 3.7.2 software interrupt (swi). . . . . . . . . . . . . . . . . . . . . . . . . . . .44 3.7.3 external interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45 3.7.4 timer interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45 3.7.5 custom peirodic interrupt (cpi) . . . . . . . . . . . . . . . . . . . . . .45 3.8 low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46 3.8.1 stop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46 3.8.2 wait . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46 3.8.3 data-retention mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47 section 4. input/output ports 4.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49 4.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49 4.3 port a . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49 4.4 port b . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50 4.5 port c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50 4.6 input/output programmingf . . . . . . . . . . . . . . . . . . . . . . . . . . .50 section 5. memory 5.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53 5.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53 5.3 rom . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53 5.4 ram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
general release speci?cation mc68HC05E1 revision 2.0 table of contents table of contents section 6. timer, phase-locked loop, and custom periodic interrupt 6.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57 6.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57 6.3 timer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58 6.3.1 timer control and status register (tcsr) $08 . . . . . . . . . .60 6.3.2 computer operating properly (cop) watchdog reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62 6.3.3 timer control register (tcr) $09 . . . . . . . . . . . . . . . . . . . .63 6.4 phase-locked loop synthesizer . . . . . . . . . . . . . . . . . . . . . . .64 6.4.1 phase-locked loop control register (pllcr) $07 . . . . . .66 6.4.2 operation during stop mode . . . . . . . . . . . . . . . . . . . . . . .68 6.4.3 noise immunity. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69 6.5 custom periodic interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69 6.5.1 custom periodic interrupt control and status register (cpicsr) $12. . . . . . . . . . . . . . . . .70 6.6 operation during stop mode . . . . . . . . . . . . . . . . . . . . . . . . .70 6.7 operation during wait mode . . . . . . . . . . . . . . . . . . . . . . . . .71 section 7. electrical specifications 7.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73 7.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73 7.3 maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .74 7.4 operating range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .75 7.5 thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .75 7.6 5.0-volt dc electrical characteristics. . . . . . . . . . . . . . . . . . . .76 7.7 3.3-volt dc electrical characteristics. . . . . . . . . . . . . . . . . . . .77 7.8 5.0-volt control timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .78 7.9 3.3-volt control timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .78 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
table of contents mc68HC05E1 revision 2.0 general release speci?cation table of contents section 8. mechanical specifications 8.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .81 8.2 mechnical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .81 8.3 package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .82 8.3.1 p suffix, plastic dip, case # 710-02 . . . . . . . . . . . . . . . . . .82 8.3.2 dw suffix, soic, case # 751f-02. . . . . . . . . . . . . . . . . . . .83 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
general release speci?cation mc68HC05E1 revision 2.0 table of contents table of contents f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
mc68HC05E1 revision 2.0 general release speci?cation list of figures general release specification mc68HC05E1 list of figures figure title page 1-1 block diagram of the mc68HC05E1 . . . . . . . . . . . . . . . . . .15 1-2 oscillator connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 2-1 single-chip mode pinout of the mc68HC05E1 . . . . . . . . . .22 2-2 self-check circuit schematic diagram . . . . . . . . . . . . . . . .23 2-3 self-check mode flowchart . . . . . . . . . . . . . . . . . . . . . . . . .25 3-1 interrupt processing flowchart. . . . . . . . . . . . . . . . . . . . . . .43 3-2 stop/wait flowcharts . . . . . . . . . . . . . . . . . . . . . . . . . . . .44 3-3 port i/o circuitry. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47 4-1 port i/o circuitry. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51 5-1 the 8 kbyte memory map of the mc68HC05E1 . . . . . . . . .54 5-2 input/output (i/o) registers . . . . . . . . . . . . . . . . . . . . . . . . .55 6-1 timer block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59 6-2 timer control and status register (tcsr) . . . . . . . . . . . . .60 6-3 timer counter register . . . . . . . . . . . . . . . . . . . . . . . . . . . .63 6-4 pll circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64 6-5 phase-locked loop control register . . . . . . . . . . . . . . . . .66 6-6 custom periodic interrupt control and status register (cpicsr) . . . . . . . . . . . . . . . . . . . .70 7-1 external interrupt mode diagram . . . . . . . . . . . . . . . . . . . . .79 7-2 stop recovery timing diagram . . . . . . . . . . . . . . . . . . . . . .79 7-3 power-on reset and reset. . . . . . . . . . . . . . . . . . . . . . . .80 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
general release speci?cation mc68HC05E1 revision 2.0 list of figures list of figures f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
mc68HC05E1 revision 2.0 general release speci?cation list of tables general release specification mc68HC05E1 list of tables table title page 2-1 operating mode conditions . . . . . . . . . . . . . . . . . . . . . . . . . .21 2-2 self-check results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25 3-1 vector address for interrupts and reset . . . . . . . . . . . . . . . .42 4-1 i/o pin functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51 6-1 rti rates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61 6-2 cop reset times. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63 6-3 loop filter bandwidth control . . . . . . . . . . . . . . . . . . . . . . . .67 6-4 ps1 and ps0 speed selects with 32.768 khz crystal . . . . . .68 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
general release speci?cation mc68HC05E1 revision 2.0 list of tables list of tables f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
mc68HC05E1 revision 2.0 general release speci?cation general description general release specification mc68HC05E1 section 1. general description 1.1 contents 1.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 1.3 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 1.4 mask options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 1.5 functional pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 1.5.1 v dd and v ss . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 1.5.2 irq (maskable interrupt request) . . . . . . . . . . . . . . . . . . . .16 1.5.3 osc1, osc2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 1.5.3.1 crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 1.5.3.2 ceramic resonator . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 1.5.3.3 external clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 1.5.4 reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 1.5.5 pa0-pa7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 1.5.6 pb0-pb7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 1.5.7 pc0-pc3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 1.5.8 xfc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 1.5.9 v ddsyn . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 1.2 introduction the mc68HC05E1 is a low-cost introduction to the m68hc05 family of microcontrollers (mcus). the hc05 cpu core has been enhanced with a 15-stage multi-functional timer and programmable phase-locked loop. the mcu is available in a 28-pin package, and has two 8-bit i/o ports and one 4-bit i/o port. the 8 kbyte memory map includes 368 bytes of ram and 4096 bytes of user rom. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
general release speci?cation mc68HC05E1 revision 2.0 general description general description 1.3 features features of the mc68HC05E1 include: ? low cost ? hc05 core ? 28-pin package ? on-chip oscillator (crystal or ceramic resonator) ? phase-locked loop (pll) synthesizer with programmable speed ? 4112 bytes of user rom (including 16 bytes of user vectors) ? 368 bytes of on-chip ram ? 15-stage multi-functional timer with programmable input ? real time interrupt circuit ? cop watchdog timer mask option ? custom periodic interrupt circuit ? 20 bidirectional i/o lines ? single-chip mode ? self-check mode ? power saving stop and wait modes ? edge-sensitive or edge- and level-sensitive interrupt trigger mask option ? stop instruction disable mask option ? illegal address reset f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
general description features mc68HC05E1 revision 2.0 general release speci?cation general description figure 1-1. block diagram of the mc68HC05E1 ? 2 accumulator index register stack pointer program counter condition code reg. osc1 osc2 oscillator internal clock select tpll oscout reset irq cop cpu m68hc05 cpu alu pc0 pc1 pc2 pc3 v dd v ss cpu registers control port a data direction register port b data direction register pb0 pb1 pb2 pb3 pb4 pb5 pb6 pb7 pa0 pa1 pa2 pa3 pa4 pa5 pa6 pa7 port c data dir reg v ddsyn xfc pll synth. processor clock timer sram 368 bytes rom 4112 bytes self-check rom 240 bytes custom periodic interrupt system system f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
general release speci?cation mc68HC05E1 revision 2.0 general description general description 1.4 mask options there are four mask options on the mc68HC05E1: stop instruction (enable/disable), irq (edge-sensitive only or edge- and level-sensitive), cop watchdog timer (enable/disable), and cpi rate (1 second, 0.5 second, or 0.25 second). note: a line over a signal name indicates an active low signal. for example, reset is active low. 1.5 functional pin description 1.5.1 v dd and v ss power is supplied to the microcontroller using these two pins. v dd is the positive supply and v ss is ground. 1.5.2 irq (maskable interrupt request) this pin has a programmable option that provides two different choices of interrupt triggering sensitivity. the options are: 1. negative edge-sensitive triggering only, or 2. both negative edge-sensitive and level-sensitive triggering. the mcu completes the current instruction before it responds to the interrupt request. when irq goes low for at least one t ilih , a logic one is latched internally to signify an interrupt has been requested. when the mcu completes its current instruction, the interrupt latch is tested. if the interrupt latch contains a logic one, and the interrupt mask bit (i bit) in the condition code register is clear, the mcu then begins the interrupt sequence. if the option is selected to include level-sensitive triggering, the irq input requires an external resistor to v dd for wire-or operation. the irq pin contains an internal schmitt trigger as part of its input to improve noise immunity. refer to 3.7 interrupts for more detail. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
general description functional pin description mc68HC05E1 revision 2.0 general release speci?cation general description note: the voltage on this pin affects the mode of operation. see section 2. operating modes . 1.5.3 osc1, osc2 these pins provide control input for an on-chip clock oscillator circuit which can optionally drive a phase-locked loop clock. a crystal, a ceramic resonator, or an external signal connects to these pins providing a system clock. the oscillator frequency is two times the internal bus rate if the pll is not used. 1.5.3.1 crystal figure 1-2 shows the recommended circuit for using a crystal. the crystal and components should be mounted as close as possible to the input pins to minimize output distortion and start-up stabilization time. 1.5.3.2 ceramic resonator a ceramic resonator may be used in place of the crystal in cost-sensitive applications. figure 1-2 shows the recommended circuit for using a ceramic resonator. the manufacturer of the particular ceramic resonator being considered should be consulted for specific information. 1.5.3.3 external clock an external clock should be applied to the osc1 input with the osc2 pin not connected. see figure 1-2 . this setup can be used if the user does not wish to run the cpu with a 32.768 khz crystal or the pll frequencies are not suitable for the application. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
general release speci?cation mc68HC05E1 revision 2.0 general description general description figure 1-2. oscillator connections 1.5.4 reset this active low pin is used to reset the mcu to a known start-up state by pulling reset low. the reset pin contains an internal schmitt trigger as part of its input to improve noise immunity. see 3.6 resets . 1.5.5 pa0-pa7 these eight i/o lines comprise port a. the state of any pin is software programmable and all port a lines are configured as input during power-on or reset. see 4.6 input/output programmingf . 1.5.6 pb0-pb7 these eight i/o lines comprise port b. the state of any pin is software programmable and all port b lines are configured as input during power-on or reset. see 4.6 input/output programmingf . < osc1 osc2 osc1 osc2 mcu mcu external clock unconnected (a) crystal/ceramic resonator (b) external clock source 330 k w 20 m w 32.768 khz oscillator connections connections 33 pf 10 pf f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
general description functional pin description mc68HC05E1 revision 2.0 general release speci?cation general description 1.5.7 pc0-pc3 these four i/o lines comprise port c. the state of any pin is software programmable and all port c lines are configured as input during power-on or reset. see 4.6 input/output programmingf . 1.5.8 xfc this pin provides a means for connecting an external filter capacitor to the synthesizer phase-locked loop filter. see 6.4 phase-locked loop synthesizer for additional information concerning this capacitor. 1.5.9 v ddsyn this pin provides a separate power connection to the pll synthesizer which should be at the same potential as v dd . note: any unused inputs and i/o ports should be tied to an appropriate logic level (either v dd or v ss ). although the i/o ports of the mc68HC05E1 do not require termination, it is recommended to reduce the possibility of static damage. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
general release speci?cation mc68HC05E1 revision 2.0 general description general description f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
mc68HC05E1 revision 2.0 general release speci?cation operating modes general release specification mc68HC05E1 section 2. operating modes 2.1 contents 2.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 2.3 single-chip mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 2.4 self-check mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 2.4.1 timer test subroutine . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 2.4.2 rom checksum subroutine. . . . . . . . . . . . . . . . . . . . . . . . .24 2.4.3 additional self-check routines . . . . . . . . . . . . . . . . . . . . . .25 2.4.3.1 self-check pll disabled . . . . . . . . . . . . . . . . . . . . . . . . .26 2.4.3.2 jump to ram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26 2.4.3.3 load ram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26 2.2 introduction the mcu has 3 modes of operation: single-chip mode, self-check mode, and test mode. table 2-1 shows the conditions required to go into each mode. table 2-1. operating mode conditions reset irq pb1 mode v ss Cv dd v ss Cv dd single chip v tst v dd self check v tst v ss factory test v tst = 2 x v dd f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
general release speci?cation mc68HC05E1 revision 2.0 operating modes operating modes 2.3 single-chip mode in single-chip mode, the address and data buses are not available externally, but there are two 8-bit i/o ports and one 4-bit i/o port. this mode allows the mcu to function as a self-contained microcontroller, with maximum use of the pins for on-chip peripheral functions. all address and data activity occurs within the mcu. single-chip mode is entered on the rising edge of reset if the irq pin is within normal operating range. figure 2-1. single-chip mode pinout of the mc68HC05E1 2.4 self-check mode the self-check mode provides an internal check to determine if the device is functional. see figure 2-2 . 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 28 27 xfc v ddsyn pa0 pa1 pa2 pa3 pa4 pa5 pa6 pa7 pc0 pc1 pc2 pc3 irq reset osc1 osc2 pb7 pb6 pb5 pb4 pb3 pb2 pb1 pb0 v dd v ss f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
operating modes self-check mode mc68HC05E1 revision 2.0 general release speci?cation operating modes figure 2-2. self-check circuit schematic diagram the self-check mode is entered on the rising edge of reset if the irq pin is at v tst , and the pb1 pin is at logic one. reset must be held low for 4064 cycles after por, or for a time t rl for any other reset. after reset, the pll is turned on (f op = 1.049 mhz) and the following tests are performed automatically: 1. i/o C functionally exercises ports a, b, and c 2. ram C counter test for each page zero ram byte 3. timer/cpi C tracks counter register and checks tof and rtif flags 4. rom C exclusive or with odd ones parity result 5. interrupts Ctests external interrupts, rti and cpi 10 pf 20 m w 1 2 3 4 5 6 7 8 9 10 19 20 21 22 23 24 25 26 27 28 irq reset pb4 pb3 pb2 pb1 pb0 v dd v ss pb5 32.768 khz 10 pf 10 k w 10 k w 4.7 k w 2n3904 v tst 11 12 13 14 15 16 17 18 pb7 pb6 1 k w v tst = 2 x v dd osc1 osc2 1 m f 10 k w v dd 0.1 m f v dd v ddsyn 330 k w pc3 xfc v ddsyn pa0 pa1 pa2 pa3 pa4 pa5 pa6 pa7 pc0 pc1 pc2 0.1 m f f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
general release speci?cation mc68HC05E1 revision 2.0 operating modes operating modes self-check results (using the leds as monitors) are shown in table 2-2 . the self-check program resides at rom location $1f00 to $1fef. the following subroutines are available to user programs and do not require any external hardware. 2.4.1 timer test subroutine this subroutine returns with the z bit cleared if any error is detected; otherwise, the z bit is set. this subroutine is called at location $1f9b. because the timer is free running and has only a divide-by-four prescaler, each timer count cannot be tested. the test sets rtie and cpie and reads the timer once every 3 counts (12 cycles) to check for correct counting. the test tracks the counter until the timer wraps around, setting the tof bit in the timer control and status register. the routine then waits for rtif=1 and cpif = 1 before returning with the rti and the cpi pending. ram location $0095 is overwritten. upon return to the users program, a=0 if the test passed. 2.4.2 rom checksum subroutine this subroutine returns with the z bit cleared if any error is detected; otherwise, the z bit is set. this subroutine is called at location $1fd1. a short routine is set up and executed in ram to compute a checksum of the entire rom pattern. the checksum byte is computed by motorola and is located in the self-check rom. upon return to the users program, x=0. if the test passed, a=0. ram locations $0090 through $0093 are overwritten. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
operating modes self-check mode mc68HC05E1 revision 2.0 general release speci?cation operating modes 2.4.3 additional self-check routines the self-check rom contains additional programs to facilitate testing and characterization of the device. figure 2-3 shows the program flow in the self-check rom. these programs are used in self-check mode (pb1=1). on power-up, the device goes into self-check mode on the rising edge of reset if the irq pin is at v tst , and the pb1 pin is at logic one. the values of pb0:pb3 after power-up determine which routine is executed from the self-check rom. only the self-check routine is intended for customer use. figure 2-3. self-check mode flowchart table 2-2. self-check results pa3 pa2 pa1 pa0 remarks 1001 bad i/o 1010 bad ram 1011 bad timer 1100 bad rom 1101 bad interrupts or irq request flashing good device all others bad device 0 indicates led is on; 1 indicates led is off. jump to ram load ram no yes yes no self-check & execute pb3=1? no yes pll disabled pll enabled pb0=1? pb2=1? power-up irq = v tst pb1=1 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
general release speci?cation mc68HC05E1 revision 2.0 operating modes operating modes 2.4.3.1 self-check pll disabled if pb2=1 and pb3=0, the self-check routine is run without turning on the pll. this allows the self-check program to run at any frequency, as determined by the value of the crystal oscillator in the self-check circuit. 2.4.3.2 jump to ram this routine is executed if pb2=0, pb1=1, and pb0=0. this routine jumps to the starting address of the ram. this is used after a program has been placed in the ram. this feature is useful for production testing where single-chip timing or port functionality is needed. 2.4.3.3 load ram this routine is entered if pb2=0, pb1=1, and pb0=1. the ldram routine does a parallel download of a program into port a using irq (data ready) and pc0 (data acknowledge) to synchronize the download with the host system. when irq (data ready) goes low, pc0 (data acknowledge) is deasserted and a byte of data is loaded from port a to ram starting at location $100. after the byte is stored in ram, pc0 is asserted as an active low data acknowledge signal to the host. the first byte downloaded must contain the total number of bytes to be downloaded (program length +1). when the download is complete, the program in ram is executed. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
mc68HC05E1 revision 2.0 general release speci?cation cpu core general release specification mc68HC05E1 section 3. cpu core 3.1 contents 3.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 3.3 registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 3.3.1 accumulator (a) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 3.3.2 index register (x) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29 3.3.3 condition code register (ccr) . . . . . . . . . . . . . . . . . . . . . .29 3.3.3.1 half carry (h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29 3.3.3.2 interrupt (i) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29 3.3.3.3 negative (n) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29 3.3.3.4 zero (z) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30 3.3.3.5 carry/borrow (c) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30 3.3.4 stack pointer (sp) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30 3.3.5 program counter (pc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31 3.4 instruction set. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31 3.4.1 register/memory instructions. . . . . . . . . . . . . . . . . . . . . . . .32 3.4.2 read-modify-write instructions . . . . . . . . . . . . . . . . . . . . . .33 3.4.3 branch instructions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34 3.4.4 bit manipulation instructions . . . . . . . . . . . . . . . . . . . . . . . .35 3.4.5 control instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36 3.5 addressing modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37 3.5.1 immediate. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37 3.5.2 direct . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37 3.5.3 extended . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37 3.5.4 re;atove . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38 3.5.5 indexed, no offset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38 3.5.6 indexed, 8-bit offset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38 3.5.7 indexed, 16-bit offset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39 3.5.8 bit set/clear . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39 3.5.9 bit test and branch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39 3.5.10 inherent . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
general release speci?cation mc68HC05E1 revision 2.0 cpu core cpu core 3.6 resets. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40 3.6.1 power-on reset (por) . . . . . . . . . . . . . . . . . . . . . . . . . . . .40 3.6.2 reset pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40 3.6.3 computer operating properly (cop) reset . . . . . . . . . . . . .40 3.6.4 illegal address reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41 3.7 interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41 3.7.1 hardware controlled interrupt sequence. . . . . . . . . . . . . . .42 3.7.2 software interrupt (swi). . . . . . . . . . . . . . . . . . . . . . . . . . . .44 3.7.3 external interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45 3.7.4 timer interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45 3.7.5 custom peirodic interrupt (cpi) . . . . . . . . . . . . . . . . . . . . . .45 3.8 low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46 3.8.1 stop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46 3.8.2 wait . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46 3.8.3 data-retention mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47 3.2 introduction this section describes the cpu core. 3.3 registers the mcu contains the registers described in the following paragraphs. 3.3.1 accumulator (a) the accumulator is a general purpose 8-bit register used to hold operands and results of arithmetic calculations or data manipulations. a 70 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
cpu core registers mc68HC05E1 revision 2.0 general release speci?cation cpu core 3.3.2 index register (x) the index register is an 8-bit register used for the indexed addressing value to create an effective address. the index register may also be used as a temporary storage area. 3.3.3 condition code register (ccr) the ccr is a 5-bit register in which the h, n, z, and c bits are used to indicate the results of the instruction just executed, and the i bit is used to enable interrupts. these bits can be individually tested by a program, and specific actions can be taken as a result of their state. each bit is explained in the following paragraphs. 3.3.3.1 half carry (h) this bit is set during add and adc operations to indicate that a carry occurred between bits 3 and 4. 3.3.3.2 interrupt (i) when this bit is set, the timer and external interrupt is masked (disabled). if an interrupt occurs while this bit is set, the interrupt is latched and processed as soon as the i bit is cleared. 3.3.3.3 negative (n) when set, this bit indicates that the result of the last arithmetic, logical, or data manipulation was negative. x 70 hinzc ccr f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
general release speci?cation mc68HC05E1 revision 2.0 cpu core cpu core 3.3.3.4 zero (z) when set, this bit indicates that the result of the last arithmetic, logical, or data manipulation was zero. 3.3.3.5 carry/borrow (c) when set, this bit indicates that a carry or borrow out of the arithmetic logical unit (alu) occurred during the last arithmetic operation. this bit is also affected during bit test and branch instructions and during shifts and rotates. 3.3.4 stack pointer (sp) the stack pointer contains the address of the next free location on the stack. during an mcu reset or the reset stack pointer (rsp) instruction, the stack pointer is set to location $00ff. the stack pointer is then decremented as data is pushed onto the stack and incremented as data is pulled from the stack. when accessing memory, the seven most significant bits are permanently set to 0000011. these seven bits are appended to the six least significant register bits to produce and address within the range of $00ff to $00c0. subroutines and interrupts may use up to 64 (decimal) locations. if 64 locations are exceeded, the stack pointer wraps around and loses the previously stored information. a subroutine call occupies two locations on the stack; an interrupt uses five locations. 00 00011 sp 12 7 0 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
cpu core instruction set mc68HC05E1 revision 2.0 general release speci?cation cpu core 3.3.5 program counter (pc) the program counter is a 13-bit register that contains the address of the next byte to be fetched. note: the hc05 cpu core is capable of addressing 16-bit locations. for this implementation, however, the addressing registers are limited to an 8k byte memory map. 3.4 instruction set the mcu has a set of 62 basic instructions. they can be divided into five different types: register/memory, read-modify-write, branch, bit manipulation, and control. the following paragraphs briefly explain each type. for more information on the instruction set, refer to the m6805 family users manual (m6805um/ad2) or the mc68hc05c4 data sheet (mc68hc05c4/d). pc 12 0 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
general release speci?cation mc68HC05E1 revision 2.0 cpu core cpu core 3.4.1 register/memory instructions most of these instructions use two operands. one operand is either the accumulator or the index register. the other operand is obtained from memory using one of the addressing modes. the jump unconditional (jmp) and jump to subroutine (jsr) instructions have no register operand. refer to the following instruction list. function load a from memory load x from memory store a in memory store x in memory add memory to a add memory and carry to a subtract memory subtract memory from a with borrow and memory to a or memory with a exclusive or memory with a arithmetic compare a with memory arithmetic compare x with memory bit test memory with a (logical compare) jump unconditional jump to subroutine mnemonic lda ldx sta stx add adc sub sbc and ora eor cmp cpx bit jmp jsr multiply mul f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
cpu core instruction set mc68HC05E1 revision 2.0 general release speci?cation cpu core 3.4.2 read-modify-write instructions these instructions read a memory location or a register, modify or test its contents, and write the modified value back to memory or to the register. the test for negative or zero (tst) instruction is an exception to the read-modify-write sequence since it does not modify the value. do not use these read-modify-write instructions on write-only locations. refer to the following list of instructions. function mnemonic increment inc decrement dec clear clr complement com negate (twos complement) neg rotate left thru carry rol rotate right thru carry ror logical shift left lsl logical shift right lsr arithmetic shift right asr test for negative or zero tst f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
general release speci?cation mc68HC05E1 revision 2.0 cpu core cpu core 3.4.3 branch instructions this set of instruction branches if a particular condition is met; otherwise, no operation is performed. branch instructions are two-byte instructions. refer to the following list for branch instructions. function mnemonic branch always bra branch never brn branch if higher bhi branch if lower or same bls branch if carry clear bcc branch if higher or same bhs branch if carry set bcs branch if lower blo branch if not equal bne branch if equal beq branch if half carry clear bhcc branch if half carry set bhcs branch if plus bpl branch if minus bmi branch if interrupt mask bit is clear bmc branch if interrupt mask bit is set bms branch if interrupt line is low bil branch if interrupt line is high bih branch to subroutine bsr f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
cpu core instruction set mc68HC05E1 revision 2.0 general release speci?cation cpu core 3.4.4 bit manipulation instructions the mcu is capable of setting or clearing any writable bit which resides in the first 256 bytes of the memory space where all port registers, port ddrs, timer, timer control, and on-chip ram reside. an additional feature allows the software to test and branch on the state of any bit within these 256 locations. the bit set, bit clear and bit test, and branch functions are all implemented with a single instruction. for test and branch instructions, the value of the bit tested is also placed in the carry bit of the condition code register. these instructions are also read-modify-write instructions. do not bit manipulate write-only locations. refer to the following list for bit manipulation instructions. function branch if bit n is set branch if bit n is clear set bit n clear bit n mnemonic brset n (n = 0. . .7) brclr n (n = 0. . .7) bset n (n = 0. . .7) bclr n (n = 0. . .7) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
general release speci?cation mc68HC05E1 revision 2.0 cpu core cpu core 3.4.5 control instructions these instructions are register reference instructions and are used to control processor operation during program execution. refer to the following list for control instructions. function transfer a to x transfer x to a set carry bit clear carry bit mnemonic tax txa sec clc set interrupt mask bit sei clear interrupt mask bit cli software interrupt swi return from subroutine rts return from interrupt rti reset stack pointer rsp no-operation nop wait wait stop stop f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
cpu core addressing modes mc68HC05E1 revision 2.0 general release speci?cation cpu core 3.5 addressing modes the mcu uses ten different addressing modes to provide the programmer with an opportunity to optimize the code for all situations. the various indexed addressing modes make it possible to locate data tables, code conversion tables, and scaling tables anywhere in the memory space. short indexed accesses are single byte instructions; the longest instructions (three bytes) permit accessing tables throughout memory. short and long absolute addressing is also included. one- or two-byte direct addressing instructions access all data bytes in most applications. extended addressing permits jump instructions to reach all memory. the term effective address (ea) is used in describing the various addressing modes. effective address is defined as the address from which the argument for an instruction is fetched or stored. 3.5.1 immediate in the immediate addressing mode, the operand is contained in the byte immediately following the opcode. the immediate addressing mode is used to access constants that do not change during program execution (e.g., a constant used to initialize a loop counter). 3.5.2 direct in the direct addressing mode, the effective address of the argument is contained in a single byte following the opcode byte. direct addressing allows the user to directly address the lowest 256 bytes in memory with a single two-byte instruction. 3.5.3 extended in the extended addressing mode, the effective address of the argument is contained in the two bytes following the opcode byte. instructions with extended addressing mode are capable of referencing arguments anywhere in memory with a single three-byte instruction. when using the motorola assembler, the user need not specify whether an instruction f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
general release speci?cation mc68HC05E1 revision 2.0 cpu core cpu core uses direct or extended addressing. the assembler automatically selects the shortest form of the instruction. 3.5.4 re;atove the relative addressing mode is only used in branch instructions. in relative addressing, the contents of the 8-bit signed offset byte (which is the last byte of the instruction) is added to the pc if, and only if, the branch conditions are true. otherwise, control proceeds to the next instruction. the span of relative addressing is from -128 to +127 from the address of the next opcode. the programmer need not calculate the offset when using the motorola assembler, since it calculates the proper offset and checks to see that it is within the span of the branch. 3.5.5 indexed, no offset in the indexed, no offset addressing mode, the effective address of the argument is contained in the 8-bit index register. this addressing mode can access the first 256 memory locations. these instructions are only one byte long. this mode is often used to move a pointer through a table or to hold the address of a frequently referenced ram or i/o location. 3.5.6 indexed, 8-bit offset in the indexed, 8-bit offset addressing mode, the effective address is the sum of the contents of the unsigned 8-bit index register and the unsigned byte following the opcode. the addressing mode is useful for selecting the kth element in an n element table. with this two-byte instruction, k would typically be in x with the address of the beginning of the table in the instruction. as such, tables may begin anywhere within the first 256 addressable locations and could extend as far as location 510. $1fe is the last location which can be accessed in this way. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
cpu core addressing modes mc68HC05E1 revision 2.0 general release speci?cation cpu core 3.5.7 indexed, 16-bit offset in the indexed, 16-bit offset addressing mode, the effective address is the sum of the contents of the unsigned 8-bit index register and the two unsigned bytes following the opcode. this address mode can be used in a manner similar to indexed, 8-bit offset except that this three-byte instruction allows tables to be anywhere in memory. as with direct and extended addressing, the motorola assembler determines the shortest form of indexed addressing. 3.5.8 bit set/clear in the bit set/clear addressing mode, the bit to be set or cleared is part of the opcode, and the byte following the opcode specifies the direct address of the byte in which the specified bit is to be set or cleared. any read/write bit in the first 256 locations of memory, including i/o, can be selectively set or cleared with a single two-byte instruction. 3.5.9 bit test and branch the bit test and branch addressing mode is a combination of direct addressing and relative addressing. the bit that is to be tested and its condition (set or clear), is included in the opcode. the address of the byte to be tested is in the single byte immediately following the opcode byte. the signed relative 8-bit offset in the third byte is added to the pc if the specified bit is set or cleared in the specified memory location. this single three-byte instruction allows the program to branch based on the condition of any readable bit in the first 256 locations of memory. the span of branching is from -128 to +127 from the address of the next opcode. the state of the tested bit is also transferred to the carry bit of the condition code register. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
general release speci?cation mc68HC05E1 revision 2.0 cpu core cpu core 3.5.10 inherent in the inherent addressing mode, all the information necessary to execute the instruction is contained in the opcode. operations specifying only the index register and/or accumulator as well as the control instructions with no other arguments are included in this mode. these instructions are one byte long. 3.6 resets the mcu can be reset three ways: by the initial power-on reset function, by an active low input to the reset pin, by a cop watchdog-timer reset, and by the iladr bit being set in the test register. 3.6.1 power-on reset (por) an internal reset is generated on power-up to allow the internal clock generator to stabilize. the power-on reset is strictly for power turn-on conditions and should not be used to detect a drop in the power supply voltage. there is a 4064 internal processor clock cycle (t cyc ) oscillator stabilization delay after the oscillator becomes active. if the reset pin is low at the end of this 4064 cycle delay, the mcu will remain in the reset condition until reset goes high. 3.6.2 reset pin the mcu is reset when a logic zero is applied to the reset input for a period of one and one-half machine cycles (t cyc ). reset is an input-only pin and will not indicate when an internal reset has occurred. 3.6.3 computer operating properly (cop) reset the mcu contains a watchdog timer that automatically times out if not reset (cleared) within a specific time by a program reset sequence. if the cop watchdog timer is allowed to timeout, an internal reset is generated to reset the mcu. because the internal reset signal is used, the mcu f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
cpu core interrupts mc68HC05E1 revision 2.0 general release speci?cation cpu core comes out of a cop reset in the same operating mode it was in when the cop time-out was generated. the cop reset function is enabled or disabled by a mask option. refer to 6.3.2 computer operating properly (cop) watchdog reset , for more information on the cop watchdog timer. 3.6.4 illegal address reset when an opcode fetch occurs from an address which is not implemented in the ram ($0090C$01ff) or rom ($0f00C$1fff), the part is automatically reset. 3.7 interrupts the mcu can be interrupted four different ways: the three maskable hardware interrupts ( irq, timer, and cpi) and the nonmaskable software interrupt instruction (swi). interrupts cause the processor to save register contents on the stack and to set the interrupt mask (i bit) to prevent additional interrupts. the rti instruction causes the register contents to be recovered from the stack and normal processing to resume. unlike reset, hardware interrupts do not cause the current instruction execution to be halted, but are considered pending until the current instruction is complete. note: the current instruction is the one already fetched and being operated on. when the current instruction is complete, the processor checks all pending hardware interrupts. if interrupts are not masked (ccr i bit clear) and the corresponding interrupt enable bit is set, the processor proceeds with interrupt processing; otherwise, the next instruction is fetched and executed. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
general release speci?cation mc68HC05E1 revision 2.0 cpu core cpu core if both an external interrupt and a timer interrupt are pending at the end of an instruction execution, the external interrupt is serviced first. the swi is executed the same as any other instruction, regardless of the i-bit state. 3.7.1 hardware controlled interrupt sequence the following three functions ( reset, stop, and wait) are not in the strictest sense an interrupt; however, they are acted upon in a similar manner. see figure 3-1 and figure 3-2 . a discussion is provided below. 1. reset - a low input on the reset input pin causes the program to vector to its starting address which is specified by the contents of memory locations $1ffe and $1fff. the i bit in the condition code register is also set. much of the mcu is configured to a known state during this type of reset as previously described in 3.6 resets . 2. stop - the stop instruction causes the oscillator to be turned off and the processor to sleep until an external interrupt ( irq) or reset occurs. 3. wait - the wait instruction causes all processor clocks to stop, but leaves the timer clock running. this rest state of the processor can be cleared by reset, an external interrupt ( irq), or timer interrupt. there are no special wait vectors for these individual interrupts. table 3-1. vector address for interrupts and reset register flag name interrupts cpu interrupt vector address n/a n/a reset reset $1ffeC$1fff n/a n/a software swi $1ffcC$1ffd n/a n/a external interrupt rq $1ffaC$1ffb tcsr tof timer over?ow timer $1ff8C$1ff9 rtif real time interrupt imer $1ff8C$1ff9 cpicsr cpif custom periodic interrupt cpi $1ff6C$1ff7 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
cpu core interrupts mc68HC05E1 revision 2.0 general release speci?cation cpu core figure 3-1. interrupt processing flowchart from reset external interrupt irq internal interrupt timer i bit set is load pc from: swi: $1ffc, $1ffd irq: $1ffa-$1ffb timer: $1ff8-$1ff9 cpi: $1ff6, $1ff7 set i bit stack pc, x, a, cc clear irq request latch restore resisters from stack cc, a, x, pc fetch next instruction execute instruction y y y n n n internal interrupt cpi y n instruction ? swi y n n instruction ? rti y n f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
general release speci?cation mc68HC05E1 revision 2.0 cpu core cpu core figure 3-2. stop/wait flowcharts 3.7.2 software interrupt (swi) the swi is an executable instruction and a non-maskable interrupt: it is executed regardless of the state of the i bit in the ccr. if the i bit is zero (interrupts enabled), swi executes after interrupts which were pending when the swi was fetched, but before interrupts generated after the swi was fetched. the interrupt service routine address is specified by the contents of memory locations $1ffc and $1ffd. turn on oscillator wait for time delay to stabilize 1. fetch reset vector or 2. service interrupt a. stack b. set i bit c. vector to interrupt routine restart processor clock 1. fetch reset vector or 2. service interrupt a. stack b. set i bit c. vector to interrupt routine y y y y y n n n n n stop wait external interrupt ( irq) reset oscillator active timer clock active processor clocks stopped stop oscillator and all clocks clear i bit timer internal interrupt cpi internal interrupt external interrupt ( irq) reset n y y f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
cpu core interrupts mc68HC05E1 revision 2.0 general release speci?cation cpu core 3.7.3 external interrupt if the interrupt mask bit (i bit) of the ccr is set, all maskable interrupts (internal and external) are disabled. clearing the i bit enables interrupts. the interrupt request is latched immediately following the falling edge of irq. it is then synchronized internally and serviced by the interrupt service routine located at the address specified by the contents of $1ffa and $1ffb. either a level-sensitive and edge-sensitive trigger, or an edge-sensitive-only trigger is available as a mask option. note: the internal interrupt latch is cleared in the first part of the interrupt service routine; therefore, one external interrupt pulse could be latched and serviced as soon as the i bit is cleared. 3.7.4 timer interrupt there are two different timer interrupt flags that cause a timer interrupt whenever they are set and enabled. the interrupt flags and enable bits are located in the timer control and status register (tcsr). either of these interrupts will vector to the same interrupt service routine, located at the address specified by the contents of memory location $1ff8 and $1ff9. see 6.3.1 timer control and status register (tcsr) $08 . 3.7.5 custom peirodic interrupt (cpi) the cpi flag and enable bits are located in the cpi control and status register (cpicsr). a cpi interrupt will vector to the interrupt service routine located at the address specified by the contents of memory location $1ff6 and $1ff7. see 6.5 custom periodic interrupt . f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
general release speci?cation mc68HC05E1 revision 2.0 cpu core cpu core 3.8 low-power modes 3.8.1 stop the stop instruction places the mcu in its lowest power consumption mode. in stop mode, the internal oscillator is turned off, halting all internal processing, including timer (and cop watchdog timer) operation. the i bit in the ccr is cleared to enable external interrupts. all other registers, including the remaining bits in the tcsr, and memory remain unaltered. all input/output lines remain unchanged. the processor can be brought out of the stop mode only by an external interrupt or reset. the stop instruction can be disabled by a mask option. when disabled, the stop instruction is executed as a nop. see 6.6 operation during stop mode . 3.8.2 wait the wait instruction places the mcu in a low-power consumption mode, but the wait mode consumes more power than the stop mode. all cpu action is suspended, but the timer remains active. an interrupt from the timer can cause the mcu to exit the wait mode. during the wait mode, the i bit in the ccr is cleared to enable interrupts. all other registers, memory, and input/output lines remain in their previous state. the timer may be enabled to allow a periodic exit from the wait mode. see 6.7 operation during wait mode . f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
cpu core low-power modes mc68HC05E1 revision 2.0 general release speci?cation cpu core 3.8.3 data-retention mode the contents of ram and cpu registers are retained at supply voltages as low as 2.0vdc. this is called the data-retention mode where the data is held, but the device is not guaranteed to operate. reset must be held low during data-retention mode. figure 3-3. port i/o circuitry data direction register bit latched output data bit i/o pin input register bit input i/o output internal hc05 connections f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
general release speci?cation mc68HC05E1 revision 2.0 cpu core cpu core f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
mc68HC05E1 revision 2.0 general release speci?cation input/output ports general release specification mc68HC05E1 section 4. input/output ports 4.1 contents 4.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49 4.3 port a . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49 4.4 port b . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50 4.5 port c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50 4.6 input/output programmingf . . . . . . . . . . . . . . . . . . . . . . . . . . .50 4.2 introduction in single-chip mode there will be 20 lines arranged as two 8-bit i/o port and one 4-bit i/o port. these ports are programmable as either inputs or outputs under software control of the data direction registers. to avoid a glitch on the output pins, write data to the i/o port data register before writing a one to the corresponding data direction register. 4.3 port a port a is an 8-bit bidirectional port which does not share any of its pins with other subsystems. the port a data register is at $0000 and the data direction register (ddr) is at $0004. reset does not affect the data registers, but clears the data direction registers, thereby returning the ports to inputs. writing a one to a ddr bit sets the corresponding port bit to output mode. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
general release speci?cation mc68HC05E1 revision 2.0 input/output ports input/output ports 4.4 port b port b is an 8-bit bidirectional port which does not share any of its pins with other subsystems. the address of the port b data register is $0001 and the data direction register (ddr) is at address $0005. reset does not affect the data registers, but clears the data direction registers, thereby returning the ports to inputs. writing a one to a ddr bit sets the corresponding port bit to output mode. 4.5 port c port c is a 4-bit bidirectional port which does not share any of its pins with other subsystems. the port c data register is at $0002 and the data direction register (ddr) is at $0006. reset does not affect the data registers, but clears the data direction registers, thereby returning the ports to inputs. writing a one to a ddr bit sets the corresponding port bit to output mode. 4.6 input/output programmingf ports a, b and c may be programmed as an input or an output under software control. the direction of the pins is determined by the state of the corresponding bit in the port data direction register (ddr). each port has an associated ddr. any port a, port b or port c pin is configured as an output if its corresponding ddr bit is set to a logic one. a pin is configured as an input if its corresponding ddr bit is cleared to a logic zero. at power-on or reset, all ddrs are cleared, which configures all port a, b, and c pins as inputs. the data direction registers are capable of being written to or read by the processor. during the programmed output state, a read of the data register actually reads the value of the output data latch and not the i/o pin. see table 4-1 and figure 4-1 . f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
input/output ports input/output programmingf mc68HC05E1 revision 2.0 general release speci?cation input/output ports figure 4-1. port i/o circuitry table 4-1. i/o pin functions r/ w* ddr i/o pin function 00 the i/o pin is in input mode. data is written into the output data latch. 0 1 data is written into the output data latch and output of the i/o pin. 1 0 the state of the i/o pin is read. 1 1 the i/o pin is in an output jmode. the output data latch is read. *r/ w is an internal signal. data direction register bit latched output data bit i/o pin input register bit input i/o output internal hc05 connections f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
general release speci?cation mc68HC05E1 revision 2.0 input/output ports input/output ports f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
mc68HC05E1 revision 2.0 general release speci?cation memory general release specification mc68HC05E1 section 5. memory 5.1 contents 5.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53 5.3 rom . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53 5.4 ram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53 5.2 introduction the mc68HC05E1 has an 8k byte memory map, consisting of user rom, user ram, self-check rom, control registers, and i/o. see figure 5-1 and figure 5-2 . 5.3 rom 4096 bytes of user rom are located from $0f00 to $1eff, with 16 additional bytes of user vectors from $1ff0 to $1fff. the self-check rom and vectors are located from $1f00 to $1fef. 5.4 ram the user ram consists of 368 bytes from location $0090 to $01ff including the stack area. the stack begins at address $00ff. the stack pointer can access 64 bytes of ram from $00ff to $00c0. using the stack area for data storage or temporary work locations requires care to prevent it from being overwritten due to stacking from an interrupt or subroutine call. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
general release speci?cation mc68HC05E1 revision 2.0 memory memory figure 5-1. the 8 kbyte memory map of the mc68HC05E1 i/o 32 bytes unused 112 bytes ram 112 bytes stack 64 bytes ram 256 bytes unused 3328 bytes user rom 4096 bytes self-check rom & vectors user vectors 16 bytes $0000 $001f $0020 $008f $0090 $00bf $00c0 $00ff $0100 $01ff $0200 $0eff $0f00 $1eff $1f00 $1fef $1ff0 $1fff 0000 0031 0032 0143 0144 0191 0192 0255 0511 0512 3840 7935 7936 8175 8176 8191 0256 3839 port a data register port b data register port c data register unused port a data direction register port b data direction register port c data direction register pll control register timer control & status register timer counter register unused cpi control & status register $00 $01 $02 $03 $04 $05 $06 $07 $08 $09 $0a $11 240 bytes . . . unused $12 reset vector (low byte) reset vector (high byte) swi vector (low byte) swi vector (high byte) irq vector (low byte) irq vector (high byte) timer vector (low byte) timer vector (high byte) cpi vector (low byte) cpi vector (high byte) unused $1ff0 $1ff5 $1ff6 $1ff7 $1ff8 $1ff9 $1ffa $1ffb $1ffc $1ffd $1ffe . . . unused $1fff unused . . . test register unused $1e $13 $1f f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
memory ram mc68HC05E1 revision 2.0 general release speci?cation memory address $00 to $001f data 76543210 $00 port a data $01 port b data $02 port c data $03 unused 0000 $04 port a ddr $05 port b ddr $06 port c ddr $07 pll control reg 0 bcs auto bwc pllon vcotst ps1 ps0 $08 timer control & status reg tof rtif tofe rtie 0 0 rt1 rt0 $09 timer counter reg $0a unused $0b unused $0c unused $0d unused $0e unused $0f unused $10 unused $11 unused $12 cpi control &status reg cpif cpie $13 unused $14 unused $15 unused $16 unused $17 unused $18 unused $19 unused $1a unused $1b unused $1c unused $1d unused $1e unused $1f unused figure 5-2. input/output (i/o) registers f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
general release speci?cation mc68HC05E1 revision 2.0 memory memory f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
mc68HC05E1 revision 2.0 general release speci?cation timer, phase-locked loop, and custom periodic interrupt general release specification mc68HC05E1 section 6. timer, phase-locked loop, and custom periodic interrupt 6.1 contents 6.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57 6.3 timer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58 6.3.1 timer control and status register (tcsr) $08 . . . . . . . . . .60 6.3.2 computer operating properly (cop) watchdog reset . . . .62 6.3.3 timer control register (tcr) $09 . . . . . . . . . . . . . . . . . . . .63 6.4 phase-locked loop synthesizer . . . . . . . . . . . . . . . . . . . . . . .64 6.4.1 phase-locked loop control register (pllcr) $07 . . . . . .66 6.4.2 operation during stop mode . . . . . . . . . . . . . . . . . . . . . . .68 6.4.3 noise immunity. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69 6.5 custom periodic interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69 6.5.1 custom periodic interrupt control and status register (cpicsr) $12. . . . . . . . . . . . . . . . .70 6.6 operation during stop mode . . . . . . . . . . . . . . . . . . . . . . . . .70 6.7 operation during wait mode . . . . . . . . . . . . . . . . . . . . . . . . .71 6.2 introduction this section describes the timer, phase-locked loop (pll), and custom periodic interrupt (cpi). f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
general release speci?cation mc68HC05E1 revision 2.0 timer, phase-locked loop, and custom periodic interrupt timer, phase-locked loop, and custom periodic 6.3 timer the timer for this device is a 15-stage multi-functional ripple counter. the features include timer over flow, power-on reset (por), real time interrupt, and cop watchdog timer. as seen in figure 6-1 , the timer is driven by the output of the clock select circuit (as determined by the value of bcs in the pllcr) then a fixed divide by four prescaler. this signal drives an 8-bit ripple counter. the value of this 8-bit ripple counter can be read by the cpu at any time by accessing the timer counter register (tcr) at address $09. a timer overflow function is implemented on the last stage of this counter, giving a possible interrupt at the rate of f op /1024. two additional stages produce the por function at f op /4064. the timer counter bypass circuitry (available only in test mode) is at this point in the timer chain. this circuit is followed by two more stages, with the resulting clock (f op /16384) driving the real time interrupt circuit. the rti circuit consists of three divider stages with a 1 of 4 selector. the output of the rti circuit is further divided by eight to drive the mask optional cop watchdog timer circuit. the rti rate selector bits, and the rti and tof enable bits and flags are located in the timer control and status register at location $08. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
timer, phase-locked loop, and custom periodic interrupt timer mc68HC05E1 revision 2.0 general release speci?cation timer, phase-locked loop, and custom periodic interrupt figure 6-1. timer block diagram cop clear mc68HC05E1 internal bus $09 tcr 7-bit counter interrupt circuit $08 tcsr rti select circuit overflow circuit detect cop watchdog timer ( ? 8) to reset logic to interrupt logic 8 8 f op f op /2 2 f op /2 10 por tcbp tcsr tcr internal processor clock tof rtif tofe rtie rt1 rt0 timer control & status register timer counter register (tcr) ? 4 f op /2 14 to f op /2 17 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
general release speci?cation mc68HC05E1 revision 2.0 timer, phase-locked loop, and custom periodic interrupt timer, phase-locked loop, and custom periodic 6.3.1 timer control and status register (tcsr) $08 the tcsr contains the timer interrupt flag, the timer interrupt enable bits, and the real time interrupt rate select bits. figure 6-2 shows the value of each bit in the tcsr when coming out of reset. figure 6-2. timer control and status register (tcsr) tof timer over flow tof is a clearable, read-only status bit and is set when the 8-bit ripple counter rolls over from $ff to $00. a cpu interrupt request will be generated if tofe is set. clearing the tof is done by writing a 0 to it. writing a 1 to tof has no effect on the bits value. reset clears tof. rtif real time interrupt flag the real time interrupt circuit consists of a three stage divider and a 1 of 4 selector. the clock frequency that drives the rti circuit is f op /2 13 (or f op /8192) with three additional divider stages giving a maximum interrupt period of 4 seconds at a crystal frequency of 32.768 khz. rtif is a clearable, read-only status bit and is set when the output of the chosen (1 of 4 selection) stage goes active. a cpu interrupt request will be generated if rtie is set. clearing the rtif is done by writing a 0 to it. writing a 1 to rtif has no effect on this bit. reset clears rtif. tofe timer over flow enable when this bit is set, a cpu interrupt request is generated when the tof bit is set. reset clears this bit. tof tofe rtie 0 0 rt1 rt0 rtif $08 0 000011 0 reset: f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
timer, phase-locked loop, and custom periodic interrupt timer mc68HC05E1 revision 2.0 general release speci?cation timer, phase-locked loop, and custom periodic interrupt rtie real time interrupt enable when this bit is set, a cpu interrupt request is generated when the rtif bit is set. reset clears this bit. rt1:rt0 real time interrupt rate select these two bits select one of four taps from the real time interrupt circuit. table 6-1 shows the available interrupt rates with several f op values. reset sets these rt0 and rt1, selecting the lowest periodic rate and therefore the maximum time in which to alter these bits if necessary. care should be taken when altering rt0 and rt1 if the time-out period is imminent or uncertain. if the selected tap is modified during a cycle in which the counter is switching, an rtif could be missed or an additional one could be generated. to avoid problems, the cop should be cleared before changing rti taps. note: in rare instances, clearing any of the timer control and status register (tcsr) flag or enable bits could result in vectoring to the reset vector rather than the timer interrupt vector if the correct precautions are not followed. do not clear any of the timer flags or enable bits (i.e., tof, tofe, rti, and rtif) with bit manipulation instructions. table 6-1. rti rates rt1:rt0 rti rates at f op frequency specified: 16.384 khz 524 khz 1.049 mhz 2.097 mhz 4.194 mhz f op 00 1 s 31.3 ms 15.6 ms 7.8 ms 3.9 ms 2 14 f op 01 2 s 62.5 ms 31.3 ms 15.6 ms 7.8 ms 2 15 f op 10 4 s 125 ms 62.5 ms 31.3 ms 15.6 ms 2 16 f op 11 8 s 250 ms 125.1 ms 62.5 ms 31.3 ms 2 17 f op f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
general release speci?cation mc68HC05E1 revision 2.0 timer, phase-locked loop, and custom periodic interrupt timer, phase-locked loop, and custom periodic example: clearing timer overflow flag (tof) bit sei sei not required if used within timer interrupt routine. lda #$73 and $tcsr or #$40 mask rtif bit sta $tcsr cli do not use cli if this code segment if used within timer interrupt routine clearing timer overflow enable (tofe) bit sei lda #$d3 and $tcsr or #$c0 mask rtif & tof sta $tcsr cli do not use cli if this code segment if used within timer interrupt routine 6.3.2 computer operating properly (cop) watchdog reset the cop watchdog timer function is implemented on this device by using the output of the rti circuit and further dividing it by eight. the minimum cop reset rates are listed in table 6-2 . if the cop circuit times out, an internal reset is generated and the normal reset vector is fetched. preventing a cop time-out is done by writing a 0 to bit 0 of address $1ff0. when the cop is cleared, only the final divide by eight stage (output of the rti) is cleared. this function is a mask option. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
timer, phase-locked loop, and custom periodic interrupt timer mc68HC05E1 revision 2.0 general release speci?cation timer, phase-locked loop, and custom periodic interrupt 6.3.3 timer control register (tcr) $09 the timer counter register is a read-only register which contains the current value of the 8-bit ripple counter at the beginning of the timer chain. this counter is clocked at f op divided by 4 and can be used for various functions including a software input capture. extended time periods can be attained using the tof function to increment a temporary ram storage location thereby simulating a 16-bit (or more) counter. figure 6-3. timer counter register the power-on cycle clears the entire counter chain and begins clocking the counter. after 4064 cycles, the power-on reset circuit is released which again clears the counter chain and allows the device to come out of reset. at this point, if reset is not asserted, the timer will start counting up from zero and normal device operation will begin. when reset is asserted anytime during operation (other than por), the counter chain will be cleared. table 6-2. cop reset times rt1:rt0 rti rates at f op frequency specified: 16.384 khz 524 khz 1.049 mhz 2.097 mhz 4.194 mhz f op 00 7 s 218.8 ms 109.4 ms 54.7 ms 27.3 ms 7 x (rti rate) 01 14 s 437.5 ms 218.8 ms 109.4 ms 54.7 ms 7 x (rti rate) 10 28 s 875.0 ms 437.5 ms 218.8 ms 109.4 ms 7 x (rti rate) 11 56 s 1.75 s 875.0 ms 437.5 ms 218.8 ms 7 x (rti rate) $09 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
general release speci?cation mc68HC05E1 revision 2.0 timer, phase-locked loop, and custom periodic interrupt timer, phase-locked loop, and custom periodic 6.4 phase-locked loop synthesizer the phase-locked loop (pll) consists of a variable bandwidth loop filter, a voltage controlled oscillator (vco), a feedback frequency divider, and a digital phase detector. the pll requires an external loop filter capacitor (typically 0.1 uf) connected between xfc and v ddsyn . this capacitor should be located as close to the chip as possible to minimize noise. v ddsyn is the supply source for the pll and should be bypassed to minimize noise. the v ddsyn bypass cap should be as close as possible to the chip. figure 6-4. pll circuit the phase detector compares the frequency and phase of the feedback frequency (t fb ) and the crystal oscillator reference frequency (t ref ) and generates the output, pcomp, as shown in figure 6-4 . the output wave-form is then integrated and amplified. the resultant dc voltage is applied to the voltage controlled oscillator. the output of the vco is divided by a variable frequency divider of 256, 128, 64, or 32 to provide the feedback frequency for the phase detector. loop filter vco phase pcomp pllout frequency divider t fb osc1 xfc crystal oscillator ps1 ps0 to clock v ddsyn detect generation circuitry clock select bcs t ref and ? 2 0.1 m f 0.1 m f f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
timer, phase-locked loop, and custom periodic interrupt phase-locked loop synthesizer mc68HC05E1 revision 2.0 general release speci?cation timer, phase-locked loop, and custom periodic interrupt to change pll frequencies, follow the procedure outlined below: 1. clear bcs to enable the low frequency bus rate, 2. clear pllon to disable the pll and select manual high bandwidth, 3. select the speed using ps1 and ps0, 4. set pllon to enable the pll, 5. wait a time of 90% t plls for the pll frequency to stabilize and select manual low bandwidth, wait another 10% t plls , 6. set bcs to switch to the high frequency bus rate. the user should not switch among the high speeds with the bcs bit set. following the procedure above will prevent possible bursts of high frequency operation during the re-configuration of the pll. the pll loop filter has two bandwidths which are automatically selected by the pll if auto=1. whenever the pll is first enabled, the wide bandwidth mode is used. this enables the pll frequency to ramp up quickly. when the output frequency is near the desired frequency, the filter is switched to the narrow bandwidth mode to make the final frequency more stable. the use of automatic bandwidth is not recommended at this time. manual bandwidth control can be done by clearing auto in the pllcr and setting the appropriate value for bwc. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
general release speci?cation mc68HC05E1 revision 2.0 timer, phase-locked loop, and custom periodic interrupt timer, phase-locked loop, and custom periodic 6.4.1 phase-locked loop control register (pllcr) $07 this read/write register contains the control bits select the pll frequency and enable/disable the synthesizer. figure 6-5. phase-locked loop control register bcs bus clock select when this bit is set, the output of the pll is used to generate the internal processor clock. when clear, the internal bus clock is driven by the crystal (osc1 ? 2). once bcs has been changed, it may take up to 1.5 osc1 cycles + 1.5 pllout cycles to make the transition. during the transition, the clock select output will be held low and all cpu and timer activity will cease until the transition is complete. before setting bcs, allow at least a time of t plls after pllon is set. reset clears this bit. auto when set, this bit selects the automatic bandwidth circuitry in the phase detect block. when clear, manual bandwidth control is selected. reset sets this bit. note: the use of automatic bandwidth is not recommended at this time. bwc bandwidth control this bit selects high bandwidth control when set, and low bandwidth control when clear. the low bandwidth driver is always enabled, so this bit determines whether the high bandwidth driver is on or off. bandwidth control is under manual control only when the auto bit is clear. when the auto bit is set, bwc acts as a read-only status bit to indicate which mode has been selected by the internal circuit. on pll start-up in automatic mode (auto=1), the high bandwidth driver is enabled (bwc=1) by internal circuitry until the pll has locked onto 0 auto bwc pllon vcotst ps1 ps0 bcs $07 0 101101 0 reset: f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
timer, phase-locked loop, and custom periodic interrupt phase-locked loop synthesizer mc68HC05E1 revision 2.0 general release speci?cation timer, phase-locked loop, and custom periodic interrupt the specified frequency. the high bandwidth driver is then disabled and bwc is cleared by internal circuitry. reset clears this bit. table 6-3 pllon pll on this bit activates the synthesizer circuit without connecting it to the control circuit. this allows the synthesizer to stabilize before it can drive the cpu clocks. when this bit is cleared, the pll is shut off. reset sets this bit. note: pllon should not be cleared while using the pll to drive the internal processor clock, i.e. when bcs is high. if the internal processor clock is driven by the pll, clearing the pllon bit would cause the internal processor clock to stop. exercise caution when using these bits. vcotst vco test this bit is used to isolate the loop filter from the vco in order to facilitate testing. when clear, the low bandwidth mode of the pll filter is disabled. when set, the loop filter operates as indicated by the values of auto and bwc. this bit is always set when auto=1 as security when running in automatic mode. reset sets this bit. note: this bit is intended for use by motorola to test and characterize the pll. the user should always have this bit set to 1. table 6-3. loop filter bandwidth control auto bwc vcotst high bandwidth low bandwidth 0 0 0 off off 0 0 1 off on 0 1 0 on off 01 1 on on 1 x 1 auto on f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
general release speci?cation mc68HC05E1 revision 2.0 timer, phase-locked loop, and custom periodic interrupt timer, phase-locked loop, and custom periodic ps1:ps0 pll synthesizer speed select these two bits select one of four taps from the pll to drive the cpu clocks. these bits are used in conjunction with pllon and bcs bits in the pll control register. these bits should not be written if bcs in the pllcr is at a logic high. reset clears ps1 and sets ps0, choosing a bus clock frequency of 1.049 mhz. note: for the standard mc68HC05E1, the 4.194 mhz bus clock frequency should never be selected, and the 2.097 mhz bus clock frequency should not be selected when running the part below v dd = 4.5 v. for the high speed mc68hsc05e1, the 4.194 mhz bus clock frequency should not be selected when running the part below v dd = 4.5 v. 6.4.2 operation during stop mode the pll is switched to low frequency bus rate and is temporarily turned off when stop is executed. coming out of stop mode with an external irq, the pll is turned on with the same configuration it had before going into stop with the exception of bcs which is reset. otherwise, the pll control register is in the reset condition. table 6-4. ps1 and ps0 speed selects with 32.768 khz crystal pa1:ps0 cpu bus clock frequency (f op ) 00 524 khz 01 1.049 mhz reset condition 10 2.097 mhz see note below 11 4.194 mhz see note below f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
timer, phase-locked loop, and custom periodic interrupt custom periodic interrupt mc68HC05E1 revision 2.0 general release speci?cation timer, phase-locked loop, and custom periodic interrupt 6.4.3 noise immunity the mcu should be insulated as much as possible from noise in the system. we recommend the following steps be taken to help prevent problems due to noise injection. 1. the application environment should be designed so that the mcu is not near signal traces which switch often, such as a clock signal, 2. the oscillator circuit for the mcu should be placed as close as possible to the osc1 and osc2 pins on the mcu, and 3. all power pins should be filtered (to minimize noise on these signals) by using bypass capacitors placed as close as possible to the mcu. see the application note designing for electromagnetic compatibility (emc) with hcmos microcontrollers , available through the motorola literature distribution center, document number an1050/d. 6.5 custom periodic interrupt the custom periodic interrupt is mask programmable to a 0.25 second, 0.5 second, or 1 second interrupt. the interrupt is generated from the 32 khz osc1 input by a 15-bit counter. this interrupt is under the control of the custom periodic interrupt control and status register located at $12. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
general release speci?cation mc68HC05E1 revision 2.0 timer, phase-locked loop, and custom periodic interrupt timer, phase-locked loop, and custom periodic 6.5.1 custom periodic interrupt control and status register (cpicsr) $12 the cpicsr contains the cpi flag and enable bits. figure 6-6 shows the location of these bits and their values after reset. figure 6-6. custom periodic interrupt control and status register (cpicsr) cpif custom periodic interrupt flag cpif is a clearable, read-only status bit and is set when the 15-bit counter changes from $7fff to $0000. a cpu interrupt request will be generated if cpie is set. clearing the cpif is done by writing a 0 to it. writing a 1 to cpif has no effect on the bits value. reset clears cpif. cpie custom periodic interrupt enable when this bit is cleared, the counter is cleared and cpi interrupts are disabled. when this bit is set, the counter starts from $0000 and a cpu interrupt request is generated when the cpif bit is set. reset clears this bit. 6.6 operation during stop mode the timer system is cleared and the cpi counter is halted when going into stop mode. when stop is exited by an external interrupt or an external reset, the internal oscillator will resume, followed by a 4064 internal processor oscillator stabilization delay. the timer system counter is then cleared and operation resumes. the cpi will continue counting once the oscillator resumes and does not wait for the oscillator to stabilize. 0 0 cpie 0000 cpif $12 0 000000 0 reset: f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
timer, phase-locked loop, and custom periodic interrupt operation during wait mode mc68HC05E1 revision 2.0 general release speci?cation timer, phase-locked loop, and custom periodic interrupt 6.7 operation during wait mode the cpu clock halts during the wait mode, but the timer and cpi remain active. if interrupts are enabled, a timer interrupt or custom periodic interrupt will cause the processor to exit the wait mode. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
general release speci?cation mc68HC05E1 revision 2.0 timer, phase-locked loop, and custom periodic interrupt timer, phase-locked loop, and custom periodic f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
mc68HC05E1 revision 2.0 general release speci?cation electrical specifications general release specification mc68HC05E1 section 7. electrical specifications 7.1 contents 7.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73 7.3 maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .74 7.4 operating range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .75 7.5 thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .75 7.6 5.0-volt dc electrical characteristics. . . . . . . . . . . . . . . . . . . .76 7.7 3.3-volt dc electrical characteristics. . . . . . . . . . . . . . . . . . . .77 7.8 5.0-volt control timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .78 7.9 3.3-volt control timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .78 7.2 introduction this section provides parametric information for the mc68HC05E1. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
general release speci?cation mc68HC05E1 revision 2.0 electrical specifications electrical speci?cations 7.3 maximum ratings maximum ratings are the extreme limits to which the mcu can be exposed without permanently damaging it. the mcu contains circuitry to protect the inputs against damage from high static voltages; however, do not apply voltages higher than those shown in the table below. keep v in and v out within the range v ss (v in or v out ) v dd . connect unused inputs to the appropriate voltage level, either v ss or v dd note: this device is not guaranteed to operate properly at the maximum ratings. refer to 7.6 5.0-volt dc electrical characteristics and 7.7 3.3-volt dc electrical characteristics for guaranteed operating conditions. rating symbol value unit supply voltage v dd C0.3 to + 7.0 v input voltage v in v ss C0.3 to v dd +0.3 v self-check mode ( irq pin only) v in v ss C0.3 to 2 x v dd +0.3 v current drain per pin excluding v dd and v ss i25ma storage temperature range t stg C65 to + 150 c f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
electrical specifications operating range mc68HC05E1 revision 2.0 general release speci?cation electrical specifications 7.4 operating range 7.5 thermal characteristics characteristic symbol value unit operating temperature range mc68HC05E1p (standard) mc68HC05E1cp (extended) mc68HC05E1mp (automotive) t a t l to t h 0 to +70 C40 to +85 C40 to +125 c characteristic symbol value unit thermal resistance plastic dip soic q ja 60 60 c/w f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
general release speci?cation mc68HC05E1 revision 2.0 electrical specifications electrical speci?cations 7.6 5.0-volt dc electrical characteristics characteristic symbol min typ max unit output voltage i load = 10.0 m a i load = C10.0 m a v ol v oh v dd C0.1 0.1 v output high voltage ( i load = C0.8 ma) pa0Cpa7, pb0Cpb7, pc0Cpc3 v oh v dd C0.8 v output low voltage ( i load = 1.6 ma) pa0Cpa7, pb0Cpb7, pc0Cpc3 v ol 0.40 v input high voltage pa0Cpa7, pb0Cpb7, pd0Cpd3, irq, reset, osc1 v ih 0.7 x v dd v dd v input low voltage pa0Cpa7, pb0Cpb7, pd0Cpd3, irq, reset, osc1 v il v ss 0.3 x v dd v xfc wide bandwidth source sink i oh i ol C50 50 C100 100 m a xfc narrow bandwidth source sink i oh i ol C1 1 C2 2 m a supply current (see notes) run f osc = 32.768 khz, f op =16.384 khz f osc = 4.2 mhz, f op = 2.1 mhz wait f osc = 32.768 khz, f op =16.384 khz f osc = 4.2 mhz, f op = 2.1 mhz stop (pll off) 25 c C40 c to +85 c (extended) i dd 100 3.5 60 0.8 2 160 5.0 100 1.2 50 180 m a ma m a ma m a m a i/o ports hi-z leakage current pb0Cpb7, pc0Cpc3, pa0Cpa7 i oz 10 m a input current reset, irq, osc1 i in 1 m a capacitance ports (as input or output) reset, irq c out c in 12 8 pf notes: 1. v dd = 5.0 vdc 10%, v ss = 0 vdc, t a = 0 c to 70 c, unless otherwise noted 2. all values shown re?ect average measurements at midpoint of voltage range at 25 c. 3. wait i dd : only timer and cpi systems active 4. run (operating) i dd , wait i dd : measured using external square wave clock source, all inputs 0.2 v from rail; no dc loads, less than 50 pf on all outputs, c l = 20 pf on osc2. 5. wait, stop i dd : all ports con?gured as inputs, v il = 0.2 vdc, v ih = v dd C0.2 vdc. 6. stop i dd is measured with osc1 = v ss . 7. standard temperature range is 0 c to 70 c. extended temperature range (C40 c to 85 c) is available. 8. wait i dd is affected linearly by the osc2 capacitance. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
electrical specifications 3.3-volt dc electrical characteristics mc68HC05E1 revision 2.0 general release speci?cation electrical specifications 7.7 3.3-volt dc electrical characteristics characteristic symbol min typ max unit output voltage i load = 10.0 m a i load = C10.0 m a v ol v oh v dd C0.1 0.1 v output high voltage ( i load = C0.2 ma) pa0Cpa7, pb0Cpb7, pc0Cpc3 v oh v dd C0.3 v output low voltage ( i load = 0.4 ma) pa0Cpa7, pb0Cpb7, pc0Cpc3 v ol 0.30 v input high voltage pa0Cpa7, pb0Cpb7, pd0Cpd3, irq, reset, osc1 v ih 0.7 x v dd v dd v input low voltage pa0Cpa7, pb0Cpb7, pd0Cpd3, irq, reset, osc1 v il v ss 0.3 x v dd v xfc wide bandwidth source sink i oh i ol C25 25 C50 50 m a xfc narrow bandwidth source sink i oh i ol C-0.5 0.5 C1 1 m a supply current (see notes) run f osc = 32.768 khz, f op =16.384 khz f osc = 2.1 mhz, f op = 1.0 mhz wait f osc = 32.768 khz, f op =16.384 khz f osc = 2.1 mhz, f op = 1.0 mhz stop (pll off) 25 c C40 c to +85 c (extended) i dd 60 1.5 30 0.3 1 90 2.0 50 0.3 30 120 m a ma m a ma m a m a i/o ports hi-z leakage current pb0Cpb7, pc0Cpc3, pa0Cpa7 i oz 10 m a input current reset, irq, osc1 i in 1 m a capacitance ports (as input or output) reset, irq c out c in 12 8 pf notes: 1. v dd = 3.3 vdc 10%, v ss = 0 vdc, t a = 0 c to 70 c, unless otherwise noted 2. all values shown re?ect average measurements at midpoint of voltage range at 25 c. 3. wait i dd : only timer and cpi systems active 4. run (operating) i dd , wait i dd : measured using external square wave clock source, all inputs 0.2 v from rail; no dc loads, less than 50 pf on all outputs, c l = 20 pf on osc2. 5. wait, stop i dd : all ports con?gured as inputs, v il = 0.2 vdc, v ih = v dd C0.2 vdc. 6. stop i dd is measured with osc1 = v ss . 7. standard temperature range is 0 c to 70 c. extended temperature range (C40 c to 85 c) is available. 8. wait i dd is affected linearly by the osc2 capacitance. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
general release speci?cation mc68HC05E1 revision 2.0 electrical specifications electrical speci?cations 7.8 5.0-volt control timing 7.9 3.3-volt control timing characteristic symbol min max unit frequency of operation crystal oscillator option external clock option f osc dc 32.768 4.2 khz mhz internal operating frequency crystal oscillator (f osc ? 2) external clock (f osc ? 2) f op dc 16.384 2.1 khz mhz cycle time t cyc 480 ns reset pulse width t rl 1.5 t cyc interrupt pulse width low (edge-triggered) (see figure 7-1 )t ilih 125 ns interrupt pulse period (see figure 7-1 )t ilil note 2 t cyc osc1 pulse width t oh , t ol 90 ns pll startup stabilization time t plls 50 ms notes: 1. v dd = 5.0 vdc 10%, v ss = 0 vdc, t a = 0 c to 70 c, unless otherwise note 2. the minimum period, t ilil , should not be less than the number of cycles it takes to execute the interrupt service routine plus 19 t cyc . characteristic symbol min max unit frequency of operation crystal oscillator option external clock option f osc dc 32.768 2.1 khz mhz internal operating frequency crystal oscillator (f osc ? 2) external clock (f osc ? 2) f op dc 16.384 1.0 khz mhz cycle time t cyc 1000 ns reset pulse width t rl 1.5 t cyc interrupt pulse width low (edge-triggered) (see figure 7-1 )t ilih 250 ns interrupt pulse period (see figure 7-1 )t ilil note 2 t cyc osc1 pulse width t oh , t ol 200 ns pll startup stabilization time t plls 100 ms notes: 1. v dd = 3.3 vdc 10%, v ss = 0 vdc, t a = 0 c to 70 c, unless otherwise note 2. the minimum period, t ilil , should not be less than the number of cycles it takes to execute the interrupt service routine plus 19 t cyc . f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
electrical specifications 3.3-volt control timing mc68HC05E1 revision 2.0 general release speci?cation electrical specifications figure 7-1. external interrupt mode diagram figure 7-2. stop recovery timing diagram irq t ilih t ilil t ilih irq1 irqn irq (mcu) normally used with wire-ored connection . . . 1ffe 1ffe 1ffe 1ffe 1fff 4 t rl t ilih osc1 1 reset irq 2 irq 3 internal clock internal address bus 4064 t cyc notes: 1. represents the internal gating of the osc1 pin 2. irq pin edge-sensitive mask option. 3. irq pin level and edge-sensitive mask option. 4. reset vector address shown for timing example. reset or interrupt vector fetch f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
general release speci?cation mc68HC05E1 revision 2.0 electrical specifications electrical speci?cations pch pcl osc1 2 reset internal processor internal address bus 1 1ffe 1fff v dd v dd threshold (1-2 v typical) t vddr 4064 t cyc t cyc t rl internal data bus 1 1ffe 1ffe 1ffe 1ffe new pc 1fff notes: 1. internal timing signal and bus information not available externally. 2. osc1 line is not meant to represent frequency. it is only used to represent time. 3. the next rising edge of the internal processor clock following the rising edge of reset initiates the reset sequence. 3 new new op code pcl pch new pc new pc op code new pc clock 1 figure 7-3. power-on reset and reset f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
mc68HC05E1 revision 2.0 general release speci?cation mechanical specifications general release specification mc68HC05E1 section 8. mechanical specifications 8.1 contents 8.2 mechnical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .81 8.3 package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .82 8.3.1 p suffix, plastic dip, case # 710-02 . . . . . . . . . . . . . . . . . .82 8.3.2 dw suffix, soic, case # 751f-02. . . . . . . . . . . . . . . . . . . .83 8.2 mechnical data 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 pa2 pa3 pa4 pa5 pa6 pa7 pc0 pc1 pc2 pc3 osc1 osc2 pb7 pb6 pb4 pb3 pb2 pb1 pb0 v dd v ss pb5 xfc v ddsyn pa0 pa1 irq reset f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
general release speci?cation mc68HC05E1 revision 2.0 mechanical specifications mechanical speci?cations 8.3 package dimensions 8.3.1 p suffix, plastic dip, case # 710-02 l j 20 pl m 114 15 28 c k 0.25(0.010) -a- -t- b d 20 pl seating plane m m b a b c d f g j k m n 36.45 13.72 3.94 0.36 0.20 2.92 0 37.21 14.2 5.08 0.56 1.52 0.38 3.43 15 1.435 0.540 0.155 0.014 0.008 0.115 0 1.465 0.560 0.200 0.022 0.060 0.015 0.135 15 0.040 1.02 notes 1. positional tolerance of leads (d), shall be within 0.25mm (0.010) at maximum material condition, in relation to seating plane and each other. 2. dimension "l" to center of leads when formed parallel. 3. dimension "b" does not include mold flash. dim millimeters min max inches min max l 0.51 1.02 0.020 0.040 15.24 bsc 0.600 bsc 2.54 bsc 0.100 bsc n g f t 0.25(0.010) m m a t h h 2.16 0.085 0.065 1.65 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
mechanical specifications package dimensions mc68HC05E1 revision 2.0 general release speci?cation mechanical specifications 8.3.2 dw suffix, soic, case # 751f-02 14 pl 0.25(0.010) m m b m r x 45 j f 114 15 28 p -a- -b- g c k -t- d 20 pl seating plane notes 1. dimensions "a" and "b" are datums and "t" is a datum surface. 2. dimensioning and tolerancing per ansi y14.5m, 1982. 3. controlling dim; millimeter. 4. dimension a and b do not include mld protrusion. 5. maximum mold protrusion 0.15 (0.006) per side. 6. 751f-01 obsolete, new standard 751f-02. a b c d f g j k m p r 17.80 7.40 2.35 0.35 0.50 1.27 bsc 0.25 0.10 0 10.05 0.25 18.05 7.60 2.65 0.49 0.90 0.32 0.25 7 10.55 0.75 0.701 0.292 0.093 0.014 0.020 0.050bsc 0010 0.004 0 0.395 0.010 0.710 0.299 0.104 0.019 0.035 0.012 0.009 7 0.415 0.029 dim millimeters min max inches min max f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
general release speci?cation mc68HC05E1 revision 2.0 mechanical specifications mechanical speci?cations f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .

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